Method and apparatus for bit demultiplexing in a wireless communication systems

ABSTRACT

A method and apparatus of bit demultiplexing for a rate 1/3 convolutional encoder in a wireless communication system, the method comprising, receiving bits from the rate-1/3 convolutional encoder, demultiplexing the received bits by distributing the bits sequentially into 3 sequences denoted as V 0 , V 1  and V 2  such that the first bit is going to the V 0  sequence, the second bit is going to the V 1  sequence and the third bit is going to the V 2  sequence and ordering the sequences such that V 0  is the first sequence, V 1  is the second sequence and V 2  is the third sequence.

CLAIM OF PRIORITY UNDER 35 U.S.C. § 119

The present Application for patent claims priority to ProvisionalApplication Ser. No. 60/731,128, entitled “WIRELESS COMMUNICATION”,filed Oct. 27, 2005, assigned to the assignee hereof, and expresslyincorporated herein by reference.

BACKGROUND

1. Field

The present disclosure relates generally to wireless communications, andmore particularly to methods and apparatus for Bit Demultiplexing in awireless communication system.

2. Background

Wireless communication systems have become a prevalent means by which amajority of people worldwide have come to communicate. Wirelesscommunication devices have become smaller and more powerful in order tomeet consumer needs and to improve portability and convenience. Theincrease in processing power in mobile devices such as cellulartelephones has lead to an increase in, demands on wireless networktransmission systems. Such systems typically are not as easily updatedas the cellular devices that communicate there over. As mobile devicecapabilities expand, it can be difficult to maintain an older wirelessnetwork system in a manner that facilitates fully exploiting new andimproved wireless device capabilities.

Wireless communication systems generally utilize different approaches togenerate transmission resources in the form of channels. These systemsmay be code division multiplexing (CDM) systems, frequency divisionmultiplexing (FDM) systems, and time division multiplexing (TDM)systems. One commonly utilized variant of FDM is orthogonal frequencydivision multiplexing (OFDM) that effectively partitions the overallsystem bandwidth into multiple orthogonal subcarriers. These subcarriersmay also be referred to as tones, bins, and frequency channels. Eachsubcarrier can be modulated with data. With time division basedtechniques, a each subcarrier can comprise a portion of sequential timeslices or time slots. Each user may be provided with a one or more timeslot and subcarrier combinations for transmitting and receivinginformation in a defined burst period or frame. The hopping schemes maygenerally be a symbol rate hopping scheme or a block hopping scheme.

Code division based techniques typically transmit data over a number offrequencies available at any time in a range. In general, data isdigitized and spread over available bandwidth, wherein multiple userscan be overlaid on the channel and respective users can be assigned aunique sequence code. Users can transmit in the same wide-band chunk ofspectrum, wherein each user's signal is spread over the entire bandwidthby its respective unique spreading code. This technique can provide forsharing, wherein one or more users can concurrently transmit andreceive. Such sharing can be achieved through spread spectrum digitalmodulation, wherein a user's stream of bits is encoded and spread acrossa very wide channel in a pseudo-random fashion. The receiver is designedto recognize the associated unique sequence code and undo therandomization in order to collect the bits for a particular user in acoherent manner.

A typical wireless communication network (e.g., employing frequency,time, and/or code division techniques) includes one or more basestations that provide a coverage area and one or more mobile (e.g.,wireless) terminals that can transmit and receive data within thecoverage area. A typical base station can simultaneously transmitmultiple data streams for broadcast, multicast, and/or unicast services,wherein a data stream is a stream of data that can be of independentreception interest to a mobile terminal. A mobile terminal within thecoverage area of that base station can be interested in receiving one,more than one or all the data streams transmitted from the base station.Likewise, a mobile terminal can transmit data to the base station oranother mobile terminal. In these systems the bandwidth and other systemresources are assigned utilizing a scheduler.

The signals, signal formats, signal exchanges, methods, processes, andtechniques disclosed herein provide several advantages over knownapproaches. These include, for example, reduced signaling overhead,improved system throughput, increased signaling flexibility, reducedinformation processing, reduced transmission bandwidth, reduced bitprocessing, increased robustness, improved efficiency, and reducedtransmission power.

SUMMARY

The following presents a simplified summary of one or more embodimentsin order to provide a basic understanding of such embodiments. Thissummary is not an extensive overview of all contemplated embodiments,and is intended to neither identify key or critical elements of allembodiments nor delineate the scope of any or all embodiments. Its solepurpose is to present some concepts of one or more embodiments in asimplified form as a prelude to the more detailed description that ispresented later.

According to one embodiment, a method is provided for receiving bitsfrom rate-1/3 convolutional encoder, demultiplexing the received bits bydistributing the bits sequentially into 3 sequences denoted as V₀, V₁and V₂ such that the first bit is going to the V₀ sequence, the secondbit is going to the V₁ sequence and the third bit is going to the V₂sequence and ordering the sequences such that V₀ is the first sequence,V₁ is the second sequence and V₂ is the third sequence.

According to yet another embodiment, a computer readable medium isdescribed which comprises a set of instructions for receiving bits fromrate-1/3 convolutional encoder, a set of instructions for demultiplexingthe received bits by distributing the bits sequentially into 3 sequencesdenoted as V₀, V₁ and V₂ such that the first bit is going to the V₀sequence, the second bit is going to the V₁ sequence and the third bitis going to the V₂ sequence and a set of instructions for ordering thesequences such that V₀ is the first sequence, V₁ is the second sequenceand V₂ is the third sequence.

According to yet another embodiment, an apparatus is described whichcomprises means for receiving bits from rate-1/3 convolutional encoder,means for demultiplexing the received bits by distributing the bitssequentially into 3 sequences denoted as V₀, V₁ and V₂ such that thefirst bit is going to the V₀ sequence, the second bit is going to the V₁sequence and the third bit is going to the V₂ sequence and means forordering the sequences such that V₀ is the first sequence, V₁ is thesecond sequence and V₂ is the third sequence.

According to one embodiment, a method is provided for receiving bitsfrom rate 1/5 turbo encoder, demultiplexing the received bits bydistributing the bits sequentially into five sequences denoted as U, V₀,V₁, V₀′ and V₁′ such that the first bit going to the U sequence, thesecond to the V₀ sequence, the third to the V₁ sequence, the fourth tothe V₀′ sequence and the fifth going to the V₁′ sequence, distributing18 tail bits numbered 0 through 17 such that tail bits numbered 0, 3, 6,9, 12 and 15 go to U sequence, tail bits numbered 1, 4 and 7 go to theV₀ sequence, tail bits numbered 2, 5 and 8 go to the V₁ sequence, tailbits 10, 13 and 16 go to the V₀′ sequence and tail bits numbered 11, 14and 17 go to the V₁′ sequence and ordering the sequences such that U isthe first sequence, V₀ is the second sequence, V₀′ is the thirdsequence, V₁ is the fourth and V₁′ is the last sequence.

According to yet another embodiment, a computer readable medium isdescribed which comprises a set of instructions for receiving bits fromrate 1/5 turbo encoder, a set of instructions for demultiplexing thereceived bits by distributing the bits sequentially into five sequencesdenoted as U, V₀, V₁, V₀′ and V₁′ such that the first bit going to the Usequence, the second to the V₀ sequence, the third to the V₁ sequence,the fourth to the V₀′ sequence and the fifth going to the V₁′ sequence,a set of instructions for distributing 18 tail bits numbered 0 through17 such that tail bits numbered 0, 3, 6, 9, 12 and 15 go to U sequence,tail bits numbered 1, 4 and 7 go to the V₀ sequence, tail bits numbered2, 5 and 8 go to the V₁ sequence, tail bits 10, 13 and 16 go to the V₀′sequence and tail bits numbered 11, 14 and 17 go to the V₁′ sequence anda set of instructions for ordering the sequences such that U is thefirst sequence, V₀ is the second sequence, V₀′ is the third sequence, V₁is the fourth and V₁′ is the last sequence.

According to yet another embodiment, an apparatus is described whichcomprises means for receiving bits from rate 1/5 turbo encoder, meansfor demultiplexing the received bits by distributing the bitssequentially into five sequences denoted as U, V₀, V₁, V₀′ and V₁′ suchthat the first bit going to the U sequence, the second to the V₀sequence, the third to the V₁ sequence, the fourth to the V₀′ sequenceand the fifth going to the V₁′ sequence, means for distributing 18 tailbits numbered 0 through 17 such that tail bits numbered 0, 3, 6, 9, 12and 15 go to U sequence, tail bits numbered 1, 4 and 7 go to the V₀sequence, tail bits numbered 2, 5 and 8 go to the V₁ sequence, tail bits10, 13 and 16 go to the V₀′ sequence and tail bits numbered 11, 14 and17 go to the V₁′ sequence and means for ordering the sequences such thatU is the first sequence, V₀ is the second sequence, V₀′ is the thirdsequence, V₁ is the fourth and V₁′ is the last sequence.

To the accomplishment of the foregoing and related ends, the one or moreembodiments comprise the features hereinafter fully described andparticularly pointed out in the claims. The following description andthe annexed drawings set forth in detail certain illustrativeembodiments of the one or more embodiments. These embodiments areindicative, however, of but a few of the various ways in which theprinciples of various embodiments may be employed and the describedembodiments are intended to include all such embodiments and theirequivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates embodiments of a multiple access wirelesscommunication system;

FIG. 2 illustrates embodiments of a transmitter and receiver in amultiple access wireless communication system;

FIGS. 3A and 3B illustrate embodiments of superframe structures for amultiple access wireless communication system;

FIG. 4A illustrates a flow diagram of a process of Bit Demultiplexingfor a rate 1/3 convolutional encoder;

FIG. 4B illustrates one or more processors for Bit Demultiplexing for arate 1/3 convolutional encoder;

FIG. 5A illustrates a flow diagram of a process of Bit Demultiplexingfor a rate 1/5 turbo encoder; and

FIG. 5B illustrates one or more processors for Bit Demultiplexing for arate 1/5 turbo encoder.

DETAILED DESCRIPTION

Various embodiments are now described with reference to the drawings,wherein like reference numerals are used to refer to like elementsthroughout. In the following description, for purposes of explanation,numerous specific details are set forth in order to provide a thoroughunderstanding of one or more embodiments. It may be evident, however,that such embodiment(s) may be practiced without these specific details.In other instances, well-known structures and devices are shown in blockdiagram form in order to facilitate describing one or more embodiments.

Referring to FIG. 1, a multiple access wireless communication systemaccording to one embodiment is illustrated. A multiple access wirelesscommunication system 100 includes multiple cells, e.g. cells 102, 104,and 106. In the embodiment of FIG. 1, each cell 102, 104, and 106 mayinclude an access point 150 that includes multiple sectors. The multiplesectors are formed by groups of antennas each responsible forcommunication with access terminals in a portion of the cell. In cell102, antenna groups 112, 114, and 116 each correspond to a differentsector. In cell 104, antenna groups 118, 120, and 122 each correspond toa different sector. In cell 106, antenna groups 124, 126, and 128 eachcorrespond to a different sector.

Each cell includes several access terminals which are in communicationwith one or more sectors of each access point. For example, accessterminals 130 and 132 are in communication base 142, access terminals134 and 136 are in communication with access point 144, and accessterminals 138 and 140 are in communication with access point 146.Controller 130 is coupled to each of the cells 102, 104, and 106.Controller 130 may contain one or more connections to multiple networks,e.g. the Internet, other packet based networks, or circuit switchedvoice networks that provide information to, and from, the accessterminals in communication with the cells of the multiple accesswireless communication system 100. The controller 130 includes, or iscoupled with, a scheduler that schedules transmission from and to accessterminals. In other embodiments, the scheduler may reside in eachindividual cell, each sector of a cell, or a combination thereof.

As used herein, an access point may be a fixed station used forcommunicating with the terminals and may also be referred to as, andinclude some or all the functionality of, a base station, a Node B, orsome other terminology. An access terminal may also be referred to as,and include some or all the functionality of, a user equipment (UE), awireless communication device, terminal, a mobile station or some otherterminology.

It should be noted that while FIG. 1, depicts physical sectors, i.e.having different antenna groups for different sectors, other approachesmay be utilized. For example, utilizing multiple fixed “beams” that eachcover different areas of the cell in frequency space may be utilized inlieu of, or in combination with physical sectors. Such an approach isdepicted and disclosed in copending U.S. patent application Ser. No.11/260,895, entitled “Adaptive Sectorization In Cellular System.”

Referring to FIG. 2, a block diagram of an embodiment of a transmittersystem 210 and a receiver system 250 in a MIMO system 200 isillustrated. At transmitter system 210, traffic data for a number ofdata streams is provided from a data source 212 to transmit (TX) dataprocessor 214. In an embodiment, each data stream is transmitted over arespective transmit antenna. TX data processor 214 formats, codes, andinterleaves the traffic data for each data stream based on a particularcoding scheme selected for that data stream to provide coded data.

The coded data for each data stream may be multiplexed with pilot datausing OFDM, or other orthogonalization or non-orthogonalizationtechniques. The pilot data is typically a known data pattern that isprocessed in a known manner and may be used at the receiver system toestimate the channel response. The multiplexed pilot and coded data foreach data stream is then modulated (i.e., symbol mapped) based on one ormore particular modulation schemes (e.g., BPSK, QSPK, M-PSK, or M-QAM)selected for that data stream to provide modulation symbols. The datarate, coding, and modulation for each data stream may be determined byinstructions performed on provided by processor 230.

The modulation symbols for all data streams are then provided to a TXprocessor 220, which may further process the modulation symbols (e.g.,for OFDM). TX processor 220 then provides N_(T) modulation symbolstreams to N_(T) transmitters (TMTR) 222 a through 222 t. Eachtransmitter 222 receives and processes a respective symbol stream toprovide one or more analog signals, and further conditions (e.g.,amplifies, filters, and upconverts) the analog signals to provide amodulated signal suitable for transmission over the MIMO channel. N_(T)modulated signals from transmitters 222 a through 222 t are thentransmitted from N_(T) antennas 224 a through 224 t, respectively.

At receiver system 250, the transmitted modulated signals are receivedby N_(R) antennas 252 a through 252 r and the received signal from eachantenna 252 is provided to a respective receiver (RCVR) 254. Eachreceiver 254 conditions (e.g., filters, amplifies, and downconverts) arespective received signal, digitizes the conditioned signal to providesamples, and further processes the samples to provide a corresponding“received” symbol stream.

An RX data processor 260 then receives and processes the N_(R) receivedsymbol streams from N_(R) receivers 254 based on a particular receiverprocessing technique to provide N_(T) “detected” symbol streams. Theprocessing by RX data processor 260 is described in further detailbelow. Each detected symbol stream includes symbols that are estimatesof the modulation symbols transmitted for the corresponding data stream.RX data processor 260 then demodulates, deinterleaves, and decodes eachdetected symbol stream to recover the traffic data for the data stream.The processing by RX data processor 218 is complementary to thatperformed by TX processor 220 and TX data processor 214 at transmittersystem 210.

RX data processor 260 may be limited in the number of subcarriers thatit may simultaneously demodulate, e.g. 512 subcarriers or 5 MHz, andsuch a receiver should be scheduled on a single carrier. This limitationmay be a function of its FFT range, e.g. sample rates at which theprocessor 260 may operate, the memory available for FFT, or otherfunctions available for demodulation. Further, the greater the number ofsubcarriers utilized, the greater the expense of the access terminal.

The channel response estimate generated by RX processor 260 may be usedto perform space, space/time processing at the receiver, adjust powerlevels, change modulation rates or schemes, or other actions. RXprocessor 260 may further estimate the signal-to-noise-and-interferenceratios (SNRs) of the detected symbol streams, and possibly other channelcharacteristics, and provides these quantities to a processor 270. RXdata processor 260 or processor 270 may further derive an estimate ofthe “operating” SNR for the system. Processor 270 then provides channelstate information (CSI), which may comprise various types of informationregarding the communication link and/or the received data stream. Forexample, the CSI may comprise only the operating SNR. In otherembodiments, the CSI may comprise a channel quality indicator (CQI),which may be a numerical value indicative of one or more channelconditions. The CSI is then processed by a TX data processor 278,modulated by a modulator 280, conditioned by transmitters 254 a through254 r, and transmitted back to transmitter system 210.

At transmitter system 210, the modulated signals from receiver system250 are received by antennas 224, conditioned by receivers 222,demodulated by a demodulator 240, and processed by a RX data processor242 to recover the CSI reported by the receiver system. The reported CSIis then provided to processor 230 and used to (1) determine the datarates and coding and modulation schemes to be used for the data streamsand (2) generate various controls for TX data processor 214 and TXprocessor 220. Alternatively, the CSI may be utilized by processor 270to determine modulation schemes and/or coding rates for transmission,along with other information. This may then be provided to thetransmitter which uses this information, which may be quantized, toprovide later transmissions to the receiver.

Processors 230 and 270 direct the operation at the transmitter andreceiver systems, respectively. Memories 232 and 272 provide storage forprogram codes and data used by processors 230 and 270, respectively.

At the receiver, various processing techniques may be used to processthe N_(R) received signals to detect the N_(T) transmitted symbolstreams. These receiver processing techniques may be grouped into twoprimary categories (i) spatial and space-time receiver processingtechniques (which are also referred to as equalization techniques); and(ii) “successive nulling/equalization and interference cancellation”receiver processing technique (which is also referred to as “successiveinterference cancellation” or “successive cancellation” receiverprocessing technique).

While FIG. 2 discusses a MIMO system, the same system may be applied toa multi-input single-output system where multiple transmit antennas,e.g. those on a base station, transmit one or more symbol streams to asingle antenna device, e.g. a mobile station. Also, a single output tosingle input antenna system may be utilized in the same manner asdescribed with respect to FIG. 2.

The transmission techniques described herein may be implemented byvarious means. For example, these techniques may be implemented inhardware, firmware, software, or a combination thereof. For a hardwareimplementation, the processing units at a transmitter may be implementedwithin one or more application specific integrated circuits (ASICs),digital signal processors (DSPs), digital signal processing devices(DSPDs), programmable logic devices (PLDs), field programmable gatearrays (FPGAs), processors, controllers, micro-controllers,microprocessors, electronic devices, other electronic units designed toperform the functions described herein, or a combination thereof. Theprocessing units at a receiver may also be implemented within one ormore ASICs, DSPs, processors, and so on.

For a software implementation, the transmission techniques may beimplemented with processors (e.g., procedures, functions, and so on)that perform the functions described herein. The software codes may bestored in a memory (e.g., memory 230, 272 x or 272 y in FIG. 2) andexecuted by a processor (e.g., processor 232, 270 x or 270 y). Thememory may be implemented within the processor or external to theprocessor.

It should be noted that the concept of channels herein refers toinformation or transmission types that may be transmitted by the accesspoint or access terminal. It does not require or utilize fixed orpredetermined blocks of subcarriers, time periods, or other resourcesdedicated to such transmissions.

Referring to FIGS. 3A and 3B, embodiments of superframe structures for amultiple access wireless communication system are illustrated. FIG. 3Aillustrates embodiments of superframe structures for a frequencydivision duplexed (FDD) multiple access wireless communication system,while FIG. 3B illustrates embodiments of superframe structures for atime division duplexed (TDD) multiple access wireless communicationsystem. The superframe preamble may be transmitted separately for eachcarrier or may span all of the carriers of the sector.

In both FIGS. 3A and 3B, the forward link transmission is divided intounits of superframes. A superframe may consist of a superframe preamblefollowed by a series of frames. In an FDD system, the reverse link andthe forward link transmission may occupy different frequency bandwidthsso that transmissions on the links do not, or for the most part do not,overlap on any frequency subcarriers. In a TDD system, N forward linkframes and M reverse link frames define the number of sequential forwardlink and reverse link frames that may be continuously transmitted priorto allowing transmission of the opposite type of frame. It should benoted that the number of N and M may be vary within a given superframeor between superframes.

In both FDD and TDD systems each superframe may comprise a superframepreamble. In certain embodiments, the superframe preamble includes apilot channel that includes pilots that may be used for channelestimation by access terminals, a broadcast channel that includesconfiguration information that the access terminal may utilize todemodulate the information contained in the forward link frame. Furtheracquisition information such as timing and other information sufficientfor an access terminal to communicate on one of the carriers and basicpower control or offset information may also be included in thesuperframe preamble. In other cases, only some of the above and/or otherinformation may be included in this superframe preamble.

As shown in FIGS. 3A and 3B, the superframe preamble is followed by asequence of frames. Each frame may consist of a same or a differentnumber of OFDM symbols, which may constitute a number of subcarriersthat may simultaneously utilized for transmission over some definedperiod. Further, each frame may operate according to a symbol ratehopping mode, where one or more non-contiguous OFDM symbols are assignedto a user on a forward link or reverse link, or a block hopping mode,where users hop within a block of OFDM symbols. The actual blocks orOFDM symbols may or may not hop between frames.

Communication between an access terminal (for example the transmittersystem 250 of FIG. 2) and an access point (for example the transmittersystem 210 of FIG. 2) occurs using a communication link and based uponpredetermined timing, system conditions, or other decision criteria. Thecommunication link may be implemented using communicationprotocols/standards such as World Interoperability for Microwave Access(WiMAX), infrared protocols such as Infrared Data Association (IrDA),short-range wireless protocols/technologies, Bluetooth® technology,ZigBee® protocol, ultra wide band (UWB) protocol, home radio frequency(HomeRF), shared wireless access protocol (SWAP), wideband technologysuch as a wireless Ethernet compatibility alliance (WECA), wirelessfidelity alliance (Wi-Fi Alliance), 802.11 network technology, publicswitched telephone network technology, public heterogeneouscommunications network technology such as the Internet, private wirelesscommunications network, land mobile radio network, code divisionmultiple access (CDMA), wideband code division multiple access (WCDMA),universal mobile telecommunications system (UMTS), advanced mobile phoneservice (AMPS), time division multiple access (TDMA), frequency divisionmultiple access (FDMA), orthogonal frequency division multiple (OFDM),orthogonal frequency division multiple access (OFDMA), orthogonalfrequency division multiple FLASH (OFDM-FLASH), global system for mobilecommunications (GSM), single carrier (1×) radio transmission technology(RTT), evolution data only (EV-DO) technology, general packet radioservice (GPRS), enhanced data GSM environment (EDGE), high speeddownlink data packet access (HSPDA), analog and digital satellitesystems, and any other technologies/protocols that may be used in atleast one of a wireless communications network and a data communicationsnetwork.

According to an embodiment, a wireless communication system comprisesencoding and modulation. A k-bit packet (generated by an appropriate MACprotocol) may be converted into sequences of modulation symbols (onesequence per sub-packet), for any value of k that satisfies at least oneof the following tow conditions: (1) k is less than Max PacketSize and(2) k is a multiple of 8. The procedures may be packet-splitting, CyclicRedundancy Check (CRC) insertion, encoding, channel interleaving,sequence repetition, scrambling and modulation.

The air link may support two basic encoding structures, namely a rate1/5 parallel turbo code and a rate 1/3 convolutional code. The rate 1/5turbo code can be used for values of k larger than 128, while the rate1/3 convolutional code can be used for values of k less than or equal to128. the encoding structure is not limited to the rate 1/5 parallelturbo code and/or rate 1/3 convolutional code. Other encoders may beimplemented in the encoding structure.

A turbo encoder is a rate 1/5 code that employs two systematic,recursive, convolutional encoders connected in parallel, with aninterleaver, the turbo interleaver, preceding the second recursiveconvolutional encoder. The two recursive convolutional codes are calledthe constituent codes of the turbo code. The outputs of the constituentencoders are punctured or repeated to achieve the desired number ofturbo encoder output bits. The turbo encoder may generate 18 tail outputbits following the encoded data output bits. The tail output bits aregenerated after the constituent encoders have been clocked k times withthe switches in the up position. The first 9 tail output bits aregenerated by clocking Constituent Encoder 1 three times with its switchin the down position while Constituent Encoder 2 is not clocked. Theconstituent encoder outputs for each bit period may e output in thesequence X, Y₀, Y₁, with the X output first. The last 9 tail output bitsare generated by clocking Constituent Encoder 2 three times with itsswitch in the down position while Constituent Encoder 1 is not clocked.The constituent encoder outputs for each bit period may be output in thesequence X′, Y₀′, Y₁′, with the X′ output first. The til bit sequenceendures that both constituent encoders achieve the all-zeros state atthe end of the encoding process.

The turbo encoder may comprise a turbo interleaver, that blockinterleave the turbo encoder input data that is fed to ConstituentEncoder 2. The turbo interleaver may be functionally equivalent to anapproach where the entire sequence of turbo interleaver input bits arewritten sequentially into an array at a sequence of addresses, and thenthe entire sequence is read out from a sequence of addresses.

According to one embodiment, the turbo or convolutional encoding may befollowed by channel interleaving, which consists of bit demultiplexingfollowed by bit permuting. The output bits generated by the rate 1/3convolutional encoder may be reordered according to the method 400 givenin FIG. 4A. FIG. 4A illustrates a flow diagram of the process 400 of bitdemultiplexing for a rate 1/3 convolutional encoder, according to anembodiment. At 402, bits from rate 1/3 convolutional encoder arereceived. At 404, the received bits are distributed sequentially into 3sequences denoted as V₀, V₁ and V₂. All of the convolutional encoderoutput bits may be demultiplexed into three sequences denoted as V₀, V₁and V₂. The encoder output bits may be sequentially distributed from theV₀ sequence to the V₂ sequence with the first bit going to the V₀sequence, the second bit going to the V₁ sequence and the third bitgoing to the V₂ sequence, the fourth to the V₀ sequence and so on. At406, the sequences are ordered such that V₀ is the first sequence and V₂is the last sequence. The V₀, V₁ and V₂ sequences may be orderedaccording to V₀, V₁ V₂.

FIG. 4B illustrates a processor 450 for bit multiplexing for 1/3convolutional encoder. The processor referred to may be electronicdevices and may comprise one or more processors to carry out themethodologies for bit multiplexing for 1/3 convolutional encoder. Aprocessor 452 is configured to receive bits from rate 1/3 convolutionalencoder are received. A processor 454 is configured to distribute thereceived bits sequentially into 3 sequences denoted as V₀, V₁ and V₂.All of the convolutional encoder output bits may be demultiplexed intothree sequences denoted as V₀, V₁ and V₂. The encoder output bits may besequentially distributed from the V₀ sequence to the V₂ sequence withthe first bit going to the V₀ sequence, the second bit going to the V₁sequence and the third bit going to the V₂ sequence, the fourth to theV₀ sequence and so on. A processor 456 is configured to order thesequences such that V₀ is the first sequence and V₂ is the lastsequence. The V₀, V₁ and V₂ sequences may be ordered according to V₀, V₁V₂. The functionality of the discrete processors 452 and 456 depicted inthe figure may be combined into a single processor 458. A memory 460 isalso coupled to the processor 458.

In an embodiment, an apparatus comprises means for receiving bits fromrate 1/3 convolutional encoder. Further, means are provided fordistributing the bits sequentially into the three sequences denoted asV₀, V₁ and V₂. further means are provide for order in the sequences. Themeans described herein may comprise one or more processors.

In yet another embodiment the output bits generated by the rate 1/5turbo encoder may be reordered according to method 500 given in FIG. 5A.FIG. 5A illustrates a flow diagram of the process 500 of bitdemultiplexing for a rate 1/5 turbo encoder, according to an embodiment.At 502, bits from rate-1/5 turbo encoder are received. At 504, thereceived bits are distributed sequentially into five sequences U, V₀,V₁, V₀′ and V₁′. All of the turbo encoder output data bits (i.e.) the 5Kbits output in the first k clock periods) may be demultiplexed into fivesequences denoted as U, V₀, V₁, V₀′ and V₁′. the encoder output bits maybe sequentially distributed from the U sequence to the V₁′ sequence withthe first encoder output bit going to the U sequence, the second to theV₀ sequence, the third to the V₁ sequence, the fourth to the V₀′sequence, the fifth to the V₁′ sequence, the sixth to the U sequence andso on. At 506, the 18 tail bits numbered 0 through 17 (i.e. the 18 bitsgenerated during the last six clock periods) may be distributed. Tailbits numbered 0, 3, 6, 9, 12 and 15 may go to the U sequence, the tailbits numbered 1, 4 and 7 may go to the V₀ sequence, the tail bitsnumbered 2, 5 and 8 may go to the V₀′ sequence, the tail bits numbered11, 14 and 17 may go to the V₁′ sequence. The tail bits of each nonsystematic stream are allocated to the corresponding sequence. At 508,the sequences U, V₀, V₁, V₀′ and V₁′ are ordered according to U V₀ V₀′V₁ V₁′. The U sequence may be the first and the V₁′ sequence may be thelast sequence.

FIG. 5B illustrates a processor 550 for bit multiplexing for 1/5 turboencoder. The processor referred to may be electronic devices and maycomprise one or more processors to carry out the methodologies for bitmultiplexing for 1/5 turbo encoder. A processor 552 is configured toreceive bits from rate-1/5 turbo encoder. A processor 554 is configuredto distribute the received bits sequentially into five sequences U, V₀,V₁, V₀′ and V₁′. All of the turbo encoder output data bits (i.e.) the 5Kbits output in the first k clock periods) may be demultiplexed into fivesequences denoted as U, V₀, V₁, V₀′ and V₁′. the encoder output bits maybe sequentially distributed from the U sequence to the V₁′ sequence withthe first encoder output bit going to the U sequence, the second to theV₀ sequence, the third to the V₁ sequence, the fourth to the V₀′sequence, the fifth to the V₁′ sequence, the sixth to the U sequence andso on. A processor 556 is configured to distribute the 18 tail bitsnumbered 0 through 17 (i.e. the 18 bits generated during the last sixclock periods). Tail bits numbered 0, 3, 6, 9, 12 and 15 may go to the Usequence, the tail bits numbered 1, 4 and 7 may go to the V₀ sequence,the tail bits numbered 2, 5 and 8 may go to the V₀′ sequence, the tailbits numbered 11, 14 and 17 may go to the V₁′ sequence. The tail bits ofeach non systematic stream are allocated to the corresponding sequence.A processor 558 is configured to order the sequences U, V₀, V₁, V₀′ andV₁′ according to U V₀ V₀′ V₁ V₁′. The U sequence may be the first andthe V₁′ sequence may be the last sequence. The functionality of thediscrete processors 552 and 558 depicted in the figure may be combinedinto a single processor 560. A memory 562 is also coupled to theprocessor 560.

In an embodiment an apparatus comprises means for receiving bits fromrate 15 turbo encoder. Further, means are provided for distributing thebits sequentially into 5 sequence denoted as U, V₀, V₁, V₀′ and V₁′.Further, means are provided for distributing 18 tail bits numbered 0through 17 and order in the five sequences as U V₀ V₀′ V₁ V₁′. The meansdescribed herein may comprise one or more processors.

Furthermore, embodiments may be implemented by hardware, software,firmware, middleware, microcode, or any combination thereof. Whenimplemented in software, firmware, middleware or microcode, the programcode or code segments to perform the necessary tasks may be stored in amachine readable medium such as a separate storage(s) not shown. Aprocessor may perform the necessary tasks. A code segment may representa procedure, a function, a subprogram, a program, a routine, asubroutine, a module, a software package, a class, or any combination ofinstructions, data structures, or program statements. A code segment maybe coupled to another code segment or a hardware circuit by passingand/or receiving information, data, arguments, parameters, or memorycontents. Information, arguments, parameters, data, etc. may be passed,forwarded, or transmitted via any suitable means including memorysharing, message passing, token passing, network transmission, etc.

Various modifications to these embodiments will be readily apparent tothose skilled in the art, and the generic principles defined herein maybe applied to other embodiments. Thus, the description is not intendedto be limited to the embodiments shown herein but is to be accorded thewidest scope consistent with the principles and novel features disclosedherein.

1. A method of bit demultiplexing for a rate 1/3 convolutional encoderin a wireless communication system, the method characterized in that:receiving bits from rate-1/3 convolutional encoder; demultiplexing thereceived bits by distributing the bits sequentially into 3 sequencesdenoted as V₀, V₁ and V₂ such that the first bit is going to the V₀sequence, the second bit is going to the V₁ sequence and the third bitis going to the V₂ sequence; and ordering the sequences such that V₀ isthe first sequence, V₁ is the second sequence and V₂ is the thirdsequence.
 2. A computer readable medium including instructions thereon,characterized in that: a set of instructions for receiving bits fromrate-1/3 convolutional encoder; a set of instructions for demultiplexingthe received bits by distributing the bits sequentially into 3 sequencesdenoted as V₀, V₁ and V₂ such that the first bit is going to the V₀sequence, the second bit is going to the V₁ sequence and the third bitis going to the V₂ sequence; and a set of instructions for ordering thesequences such that V₀ is the first sequence, V₁ is the second sequenceand V₂ is the third sequence.
 3. An apparatus operable in a wirelesscommunication system, the apparatus characterized in that: means forreceiving bits from rate-1/3 convolutional encoder; means fordemultiplexing the received bits by distributing the bits sequentiallyinto 3 sequences denoted as V₀, V₁ and V₂ such that the first bit isgoing to the V₀ sequence, the second bit is going to the V₁ sequence andthe third bit is going to the V₂ sequence; and means for ordering thesequences such that V₀ is the first sequence, V₁ is the second sequenceand V₂ is the third sequence.
 4. A method of bit demultiplexing for arate 1/5 turbo encoder in a wireless communication system, the methodcharacterized in that: receiving bits from rate 1/5 turbo encoder;demultiplexing the received bits by distributing the bits sequentiallyinto five sequences denoted as U, V₀, V₁, V₀′ and V₁′ such that thefirst bit going to the U sequence, the second to the V₀ sequence, thethird to the V₁ sequence, the fourth to the V₀′ sequence and the fifthgoing to the V₁′ sequence; distributing 18 tail bits numbered 0 through17 such that tail bits numbered 0, 3, 6, 9, 12 and 15 go to U sequence,tail bits numbered 1, 4 and 7 go to the V₀ sequence, tail bits numbered2, 5 and 8 go to the V₁ sequence, tail bits 10, 13 and 16 go to the V₀′sequence and tail bits numbered 11, 14 and 17 go to the V₁′ sequence;and ordering the sequences such that U is the first sequence, V₀ is thesecond sequence, V₀′ is the third sequence, V₁ is the fourth and V₁′ isthe last sequence.
 5. A computer readable medium including instructionsthereon, characterized in that: a set of instructions for receiving bitsfrom rate 1/5 turbo encoder; a set of instructions for demultiplexingthe received bits by distributing the bits sequentially into fivesequences denoted as U, V₀, V₁, V₀′ and V₁′ such that the first bitgoing to the U sequence, the second to the V₀ sequence, the third to theV₁ sequence, the fourth to the V₀′ sequence and the fifth going to theV₁′ sequence; a set of instructions for distributing 18 tail bitsnumbered 0 through 17 such that tail bits numbered 0, 3, 6, 9, 12 and 15go to U sequence, tail bits numbered 1, 4 and 7 go to the V₀ sequence,tail bits numbered 2, 5 and 8 go to the V₁ sequence, tail bits 10, 13and 16 go to the V₀′ sequence and tail bits numbered 11, 14 and 17 go tothe V₁′ sequence; and a set of instructions for ordering the sequencessuch that U is the first sequence, V₀ is the second sequence, V₀′ is thethird sequence, V₁ is the fourth and V₁′ is the last sequence.
 6. Anapparatus operable in a wireless communication system, the apparatuscharacterized in that: means for receiving bits from rate 1/5 turboencoder; means for demultiplexing the received bits by distributing thebits sequentially into five sequences denoted as U, V₀, V₁, V₀′ and V₁′such that the first bit going to the U sequence, the second to the V₀sequence, the third to the V₁ sequence, the fourth to the V₀′ sequenceand the fifth going to the V₁′ sequence; means for distributing 18 tailbits numbered 0 through 17 such that tail bits numbered 0, 3, 6, 9, 12and 15 go to U sequence, tail bits numbered 1, 4 and 7 go to the V₀sequence, tail bits numbered 2, 5 and 8 go to the V₁ sequence, tail bits10, 13 and 16 go to the V₀′ sequence and tail bits numbered 11, 14 and17 go to the V₁′ sequence; and means for ordering the sequences suchthat U is the first sequence, V₀ is the second sequence, V₀′ is thethird sequence, V₁ is the fourth and V₁′ is the last sequence.